Clocks in Sequential Logic

• Purpose: Clocks control when state elements (memory elements) update their values in sequential circuits.
• Clock Signal: A free-running signal with a fixed cycle time.
  • Clock period (T): Time for one complete high + low cycle.
  • Clock frequency (f): f=1/T

Edge-Triggered Clocking

• Definition: State changes occur only on a clock edge (rising or falling).
• Advantages:
  • Sampling is effectively instantaneous.
  • Avoids timing issues if signals change slightly out of sync.
• Implementation: The choice of active edge depends on technology but does not affect design concepts.

State Elements and Synchronous Systems

• State element: Memory element that stores a value.
• Synchronous system: Uses a clock; data signals are read/written only when the clock indicates signals are stable.
• Constraints:
  • Inputs to combinational logic must be valid before the active clock edge.
  • The clock period must be long enough for all combinational outputs to stabilize.
• Operation:
  1. State elements provide inputs to combinational logic.
  2. Combinational logic produces outputs.
  3. Outputs are sampled by state elements at the next active clock edge.

Special Considerations

• Write signals: Some state elements update conditionally. Write signals must be gated with the clock to ensure updates occur only on the active edge.