Memory Elements in Sequential Logic

1. Sequential Logic and State

• Memory elements store state: output depends on both input and previously stored value.
• All blocks containing memory elements are sequential circuits.

2. Latches and Flip-Flops

S-R Latch (Unclocked)

• Built from cross-coupled NOR gates.
• Stores a value: Q and Q̅ are complements.
• Operation:
  • S = Set → Q = 1, Q̅ = 0
  • R = Reset → Q = 0, Q̅ = 1
  • S = R = 0 → maintains previous state
• S = 1 AND R = 1 → invalid/metastable state.

D Latch (Clocked)

• Input: D (data), C (clock)
• Transparent latch: when C asserted, Q follows D; when C deasserted, Q holds last value.

D Flip-Flop

• Built from master-slave D latches.
• Edge-triggered: Q updates only on a clock edge (rising or falling).