Memory Systems: SRAM, DRAM, and Error Correction

Registers and register files are the building blocks of small memories, but larger memory structures rely on SRAMs (Static RAM) or DRAMs (Dynamic RAM).

1. Static RAM (SRAM)

Definition:

• Memory that stores data statically using flip-flops; retains data as long as power is applied.

Characteristics:

• Fast access (2–4 ns for small, high-speed parts).
• Expensive per bit, less dense than DRAM.
• Typical configuration:
  • Height = number of entries
  • Width = number of bits per entry
  • Example: A 2M X 16 SRAM showing the 21 address lines (2M = 2^21) and 16 data inputs, the 3 control lines, and the 16 data outputs

• Four three-state buffers are used to form a multiplexor
  • Only one of the four Select inputs can be asserted. A three-state buffer with a deasserted Output enable has a high-impedance output that allows a three-state buffer whose Output enable is asserted to drive the shared output line.

• The basic structure of a 4 X 2 SRAM consists of a decoder that selects which pair of cells to activate
  • The activated cells use a three-state output connected to the vertical bit lines that supply the requested data. The address that selects the cell is sent on one of a set of horizontal address lines, called word lines. For simplicity, the Output enable and Chip select signals have been omitted, but they could easily be added with a few AND gates.

Control Signals:

• Chip Select (CS): Activates the memory chip
• Output Enable (OE): Controls whether data is driven onto the output lines (useful for shared buses)
• Write Enable (WE): Triggers write operation; must meet setup/hold times and pulse width requirements